As integrated circuit memories become larger and more complex, it becomes extremely difficult to fabricate a memory array which is entirely free of defective bits. If it be required that a memory be entirely defect-free to be acceptable, the yield in manufacture of acceptable large memories tends to be very low.
As a consequence, increasing consideration is being given to including, in a memory, redundant cells which can be substitued for defective cells whereby there may be achieved a memory which has defect-free cells at operative sites.
There has been hitherto a number of schemes proposed which provide for the substitution of defect-free redundant cells for defective cells. Typical are the schemes described in U.S. Pat. Nos. 3,753,235, 3,753,244 and 4,047,163 but these typically have involved the necessity of considerable additional circuitry.
Considerations which we have viewed as important for a defect-tolerant memory are as follows:
1. The entire memory would all be on one chip.
2. The extra cells and circuitry should not interfere with the function of an otherwise good chip, i.e., if a chip is fault-free without utilizing spares, no steps should be required to disable spares.
3. The testing and substitution should be possible by a fast, simple, high-yield process to avoid long turnaround times and/or low repair yield. Advantageously, both the disabling of standard rows and columns having defective cells and the substitution of spare rows and columns should be done by a similar technique, preferably by a process involving making disconnections rather than connections.
4. The incorporation of spares should result in essentially no performance degradation to the basic circuit. Preferably the use or nonuse of spares should change the characteristics little as viewed from the external terminals of the memory.
5. The provision for spares should not significantly increase the total area needed for the chip.